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Make and Makefiles

by Anu Rao

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Why Use make and makefiles?

• simplifies management, compliation and linking of codes with several subroutines/components
• checks dependencies to see if source file .c (or .f) is dated later than object file .o ; if yes, then it recompiles the source code
• easy to set it up to "make" different versions of one's code

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Running make

To run make, at the Linux prompt simply type

make

By default it looks for a makefile with the name makefile or Makefile, otherwise you can specify the alternate name of your makefile with

make -f altfilename

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Sample Makefiles

Let's say we have 3 pieces of C code: our main program main.c with two subroutines contained in sub1.c and sub2.c, that use the library /usr/lib/mylib.a. Then a simple, bare-bones, nothing-too-fancy makefile for this code would look like:

progex: main.o sub1.o sub2.o /usr/lib/mylib.a
        cc -o progex main.o sub1.o sub2.o /usr/lib/mylib.a
  ^
 /|\
  |____important: TAB necessary

main.o: main.c
        cc -c main.c
sub1.o: sub1.c
        cc -c sub1.c
sub2.o: sub2.c
        cc -c sub2.c

where progex is the name of the executable for our code. Note that every command has to begin with a TAB.

Here is another generic Makefile with a some simple options, for C or FORTRAN code.

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Macros

Macros allow one to store commands or long names in variable names. Macros are defined (in capital letters) in makefiles by

MACRONAME= text string and referenced within a makefile by $(MACRONAME). Note that you will never get an error message for an undefined macro.

There are built-in macros, such as CC, LD, FC, F77. To view the default built-ins, type

make -p or make -fp - < /dev/null  

Generally options to cc are stored in CFLAGS, options to f77 are stored in FFLAGS, etc.

One can also use macros for string substitution. Here is as example: define SRCS = main.c defs.c redraw.c close.c. Then $(SRCS:.c.o) is a macro for main.o defs.o redraw.o close.o.

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Suffix Rules

If a *.o file is specified, then suffix rules dictate that it could have come from *.f, *.c. So, using macros and suffix rules we can rewrite our simple, bare-bones, nothing-too fancy makefile for main.c, sub1.c, sub2.c (from above) as:

OBJS = main.o sub1.o sub2.o
LIB = /usr/lib/mylib.a
progex: $(OBJS) $(LIB)
        cc -o progex $(OBJS) $(LIB)

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Status and Debugging

make -n

runs through the motions without actually executing any commands

make -s

executes all the commands but does not echo them

make -d

debug mode

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Helpful Hints/Notes for make

• make assumes that the code resides in the same directory as the makefile
• begin every command with a TAB
• "#" is the comment character
• you can define shell ENVIRONMENT variables inside makefiles
• when dealing with header files *.h, one needs to specify them explicitly as a dependency
• for large projects with multiple directories, one may want to consider
  • recursive make
  • directories as internal macros
  • setting the VPATH macro